Abstract: A new technique is

introduced that combines the advantages of the output wired CMOS logic with the

majority gate. The concept of majority gate is of utmost importance because it

helps in reducing the delay produced in the circuits and output wired CMOS

logic helps in reducing the transistor count. The adder circuits i.e. full

adder, ripple carry adder and carry look ahead adder have been simulated using

tanner tool for 130nm channel length. The results obtained show that this new

technique has an advantage of delay reduction and less power consumption as

compared to the conventional design. Also, the transistor count for the designs

is less than the conventional design transistor count.

Keywords – Adder, Complementary

Metal Oxide Semiconductor (CMOS), full adder, Majority gate,ripple carry adder,

carry look ahead adder

I.

Introduction

One of the basic fundamental

arithmetic operation is addition. It is extensively used in application

specific systems. The adder cell designed is based on majority gate and output

wired CMOS logic. It helps in dealing with issues of power consumption, delay

in output, transistor count and the area required for the design.

There are different implementation

techniques for threshold gate based logic design. Threshold gate can be

implemented using capacitive threshold logic , output wired CMOS inverter ,

MOS-NDR based monostable bistable transistor logic .In this paper, we have

designed one bit full adder CMOS circuit using output wired CMOS logic based

majority gate. Further, the other adder circuits i.e. 4-bit ripple carry adder

and 2 bit carry look ahead adder circuit has been designed using the same

logic. On performing the comparative analysis, the simulation results show that

the proposed designs have less delay and reduced power consumption.

Other sections in the paper include:

Section II : Description of Concept of majority gate

Section III :Discussing concept of output wired CMOS logic

Section IV: Design of one bit full adder using output wired CMOS logic based majority

gate

Section V: Design of ripple carry adder using output wired CMOS logic based

majority gate

Section VI: Design of carry look ahead adder using output wired CMOS logic based majority

gate

Section VII : Comparison of

proposed designs with

conventional designs

Section VIII: Conclusion.

II.

concept

of majority gate

A

majority gate is a logical gate used in circuit complexity and other applications

of Boolean circuits. In case of majority gate the output will be ‘1’ if over

half of the inputs are ‘1’otherwise it will be ‘0’. As shown in the figure 1,

there are three inputs a, b and c and either of the two inputs are passed

through the AND logic gate and the output obtained respectively are passed

through the OR logic gate. Thus, the logic produced is:

(1)

Fig.

1 3 input majority gate

As

shown infig.2, the majority gate usually consists of odd number of inputs represented

as “w”.

Fig

2 Majority gate function

In other words, the majority gate can be

called a special case of threshold gate where the threshold value is equal to

half of input plus one.

Mathematically,

III.

concept

of output wired logic

A wired logic connection is a logic gate that

implements Boolean algebra (logic) using only passive elements like resistors,

capacitors. It also uses diode for the logic implementation when it’s not

behaving as an active device means when it has no negative differential

resistance. A wired logic connection can create an AND or OR gate. Here,

instead of AND and OR gate we have used CMOS as an element that helps to form

the output wired CMOS logic.